supertex inc. supertex inc. www.supertex.com lnd01 doc.# dsfp-lnd01b031414 general descriptionthe lnd01 is a low threshold, depletion-mode (normally-on) transistor utilizing an advanced lateral dmos structure and supertexs well-proven silicon-gate manufacturing process. this combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coeficient inherent in mos devices. characteristic of all mos structures, this device is free from thermal runaway and thermally-induced secondary breakdown. the body of the transistor is connected to the gate pin. the channel is therefore being pinched off by both the gate and body. the gate pin will have a diode connected to the drain terminal and another diode connected to the source terminal. absolute maximum ratings parameter value drain-to-source voltage bv dsx source-to-drain voltage bv sdx gate-to-source voltage -12v to +0.6v gate-to-drain voltage -12v to +0.6v operating temperature range -25c to +125c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. ordering information part number package option packing LND01K1-G 5-lead sot-23 2500/reel -g indicates package is rohs compliant (green) product marking 5-lead sot-23 nduw w = code for week sealed = ?green? packaging packages may or may not include the following marks: si or 5-lead sot-23 lateral n-channeldepletion-mode mosfet 3 (n/c) 2 (gate) 1 (n/c) 4 (drain) 5 (source) pin coniguration features ? bi-directional ? low on-resistance ? low input capacitance ? fast switching speeds ? high input impedance and high gain ? low power drive requirement ? ease of paralleling applications ? normally-on switches ? solid state relays ? converters ? constant current sources ? analog switches product summary bv dsx /bv sdx (min v) r ds(on) /r sd(on) (max ) i dss /i sdd (min ma) 9.0 1.4 300 downloaded from: http:///
supertex inc. www.supertex.com 2 lnd01 doc.# dsfp-lnd01b031414 electrical characteristics (@25 c unless otherwise speciied) sym parameter min typ max unit conditions bv dsx drain-to-source breakdown voltage 9.0 - - v v gs = -3.0v, i ds = 10a bv sdx source-to-drain breakdown voltage 9.0 - - v v gd = -3.0v, i sd = 10a v gs(off) gate-to-source off voltage -0.8 - -3.0 v v ds = 9.0v, i ds = 1.0a v sg(off) source-to-gate off voltage -0.8 - -3.0 v v sd = 9.0v, i sd = 1.0a v gs gate-to-source diode -12 - 0.6 v i gs = 1.0a v gd gate-to-drain diode -12 - 0.6 v i gd = 1.0a i ds(off) drain-to-source leakage current - - 1.0 a v gs = -3.0v, v ds = 9.0v i sd(off) source-to-drain leakage current - - 1.0 a v gd = -3.0v, v sd = 9.0v i dss saturated drain-to-source current 300 - - ma v gs = 0v, v ds = 9.0v i sdd saturated source-to-drain current 300 - - ma v gd = 0v, v sd = 9.0v r ds(on) static drain-to-source on-state resistance - 0.9 1.4 v gs = 0v, i ds = 100ma r sd(on) static source-to-drain on-state resistance - 0.9 1.4 v gd = 0v, i sd = 100ma g fs forward transconductance 200 - - mmho v ds = 9.0v, i ds = 50ma c iss input capacitance - 46 - pf v gs = -3.0v v ds = 5.0v f = 1.0mhz c oss common source output capacitance - 32 - c rss reverse transfer capacitance - 23 - t d(on) turn-on delay time - 3.8 - ns v dd = 9.0v, i ds = 100ma r gen = 25 t r rise time - 11 - t d(off) turn-off delay time - 1.0 - t f fall time - 6.4 - notes: 1. all d.c. parameters 100% tested at 25 c unless otherwise stated. (pulse test: 300s pulse, 2% duty cycle.) 2. all a.c. parameters sample tested. notes: ? i d (continuous) is limited by max rated t j . thermal characteristics package i d (continuous) ? (ma) i d (pulsed) (ma) power dissipation @t a = 25c (w) ja (c/w) 5-lead sot-23 (k1) 330 600 0.36 253 switching waveforms and test circuit 90% 10% 90% 90% 10% 10% pulse generator vdd r l output d.u.t. t (on) t d(on) t (off) t d(off) t r input 0v input -3.0v vdd output 0v r gen t f source gate drain downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc . does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//www .supertex.com) ?2014 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 3 lnd01 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-lnd01b031414 5-lead sot-23 package outline (k1) 2.90x1.60mm body, 1.45mm height (max), 0.95mm pitch symbol a a1 a2 b d e e1 e e1 l l1 l2 1 dimension (mm) min 0.90* 0.00 0.90 0.30 2.75* 2.60* 1.45* 0.95 bsc 1.90 bsc 0.30 0.60 ref 0.25 bsc 0 o 5 o nom - - 1.15 - 2.90 2.80 1.60 0.45 4 o 10 o max 1.45 0.15 1.30 0.50 3.05* 3.00* 1.75* 0.60 8 o 15 o jedec registration mo-178, variation aa, issue c, feb. 2000. * this dimension is not speciied in the jedec drawing. drawings not to scale. supertex doc. #: dspd-5sot23k1, version a041309. 1 5 d seating plane gauge plane l l1 l2 top vi ew side view vi ew a - a vi ew b view b 1 e1 e a a2 a1 a a seating plane e b note 1 (index area d/2 x e/2) e1 note: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. downloaded from: http:///
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